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83948AYI-147LF PDF预览

83948AYI-147LF

更新时间: 2024-02-13 11:47:57
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
17页 361K
描述
Low Skew, 1-to-1 Differential to-

83948AYI-147LF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Lifetime Buy零件包装代码:TQFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:2.31
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:11129697Samacsys Pin Count:32
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat Packages
Samacsys Footprint Name:PRG32Samacsys Released Date:2020-01-30 10:31:48
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:83948输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.015 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:12
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):4.4 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.16 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

83948AYI-147LF 数据手册

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Low Skew, 1-to-1 Differential-  
83948I-147  
Data Sheet  
to-LVCMOS/ LVTTL Fanout Buffer  
General Description  
Features  
The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT-  
TL Fanout Buffer. The 83948I-147 has two selectable clock inputs.  
The CLK, nCLK pair can accept most standard differential input lev-  
els. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.  
The low impedance LVCMOS/LVTTL outputs are designed to drive  
50series or parallel terminated transmission lines. The effective fa-  
nout can be increased from 12 to 24 by utilizing the ability of the out-  
puts to drive two series terminated lines.  
Twelve LVCMOS/LVTTL outputs  
Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input  
CLK/nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
LVCMOS_CLK supports the following input types:  
LVCMOS, LVTTL  
Output frequency: 350MHz  
The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V  
core/2.5V output operating supply modes. Guaranteed output and  
part-to-part skew characteristics make the 83948I-147 ideal for those  
clock distribution applications demanding well defined performance  
and repeatability.  
Additive phase jitter, RMS: 0.14ps (typical)  
Output skew: 100ps (maximum), 3.3V 5%  
Part-to-part skew: 1ns (maximum), 3.3V 5%  
Operating supply modes:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
2.5V/2.5V  
-40°C to 85°C ambient operating temperature  
Lead-free (RoHS 6) packaging  
Block Diagram  
Pin Assignment  
CLK_EN  
D
Q
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
CLK_SEL  
GND  
24  
23  
22  
21  
20  
LVCMOS_CLK  
1
Q0  
LVCMOS_CLK  
CLK  
Q4  
CLK  
nCLK  
0
VDDO  
Q5  
Q1  
nCLK  
CLK_SEL  
Q2  
CLK_EN  
GND  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Q11  
OE  
VDD  
Q6  
19  
18  
17  
VDDO  
Q7  
GND  
9
10 11 12 13 14 15 16  
83948I-147  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
OE  
©2016 Integrated Device Technology, Inc  
1
Revision D March 30, 2016  

83948AYI-147LF 替代型号

型号 品牌 替代类型 描述 数据表
83948AYI-147LFT IDT

完全替代

Low Skew, 1-to-1 Differential to-
83948AYILFT IDT

类似代替

Low Skew, 1-to-12 Differential-to- LVCMOS/LVTTL Fanout Buffer

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83948I-147 IDT

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