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810251AGILF PDF预览

810251AGILF

更新时间: 2024-01-29 17:30:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路石英晶振压控振荡器晶体
页数 文件大小 规格书
15页 238K
描述
VCXO and Synchronous Ethernet Jit ter At tenuator

810251AGILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.9
其他特性:ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:25 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:40 mA最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

810251AGILF 数据手册

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810251I Data Sheet  
Schematic Example  
Figure 1 shows an example of the 810251I application schematic. In  
this example, the device is operated either at VDD = 3.3V or 2.5V.  
The decoupling capacitors should be located as close as possible to  
the power pin. The input is driven by an LVCMOS driver. An optional  
3-pole filter can also be used for additional spur reduction. It is  
recommended that the loop filter components be laid out for the  
3-pole option. This will also allow the 2-pole filter to be used.  
3-pole loop filter example - (optional)  
R3  
LF0  
LF1  
Rs  
TBD  
VDD  
TBD  
VDDO  
Cp  
C3  
C1  
Cs  
TBD  
TBD  
0.1u  
TBD  
C2  
0.1u  
VDD  
VDD  
R2  
9
10  
11  
12  
13  
14  
15  
16  
8
10  
GND  
VDD  
VDDA  
OE  
VDDO  
Q
Reserv ed  
GND  
PLL_SEL  
XTAL_OU T  
XTAL_I N  
VDDA  
7
6
5
4
3
2
1
XTAL_OU T  
XTAL_I N  
GND  
LF0  
LF1  
C5  
SPARE  
X2  
C30  
0.01u  
C45  
10u  
VDD  
CLK_IN  
Rs  
1K  
C6  
Cp  
SPARE  
Cs  
0.001 uF  
Zo = 50  
10uF  
C4  
0.1u  
U1  
R4  
33  
Logic Control Input Examples  
LVCMOS_Receiv er  
2-pole loop filter  
Set Logic  
Input to  
'1'  
Set Logic  
VDD  
VDD  
Input to  
'0'  
Q1  
R1  
33  
Zo = 50  
RU1  
1K  
RU2  
Not Install  
VDD=VDDO=3.3V  
LVCMOS_Driv er  
To Logic  
Input  
To Logic  
Input  
pins  
pins  
RD1  
Not Install  
RD2  
1K  
Figure 1. P.C. 810251I Schematic Example  
©2016 Integrated Device Technology, Inc  
9
Revision B March 3, 2016  

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