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80C32-44R PDF预览

80C32-44R

更新时间: 2024-10-27 22:46:23
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TEMIC 微控制器
页数 文件大小 规格书
20页 227K
描述
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller

80C32-44R 数据手册

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80C32/80C52  
MATRA MHS  
There are three ways to terminate the Idle mode.  
Activation of any enabled interrupt will cause PCON.0 to  
be cleared by hardware, terminating Idle mode. The  
interrupt is serviced, and following RETI, the next  
instruction to be executed will be the one following the  
instruction that wrote 1 to PCON.0.  
Power Down Mode  
The instruction that sets PCON.1 is the last executed prior  
to entering power down. Once in power down, the  
oscillator is stopped. The contents of the onchip RAM and  
the Special Function Register is saved during power down  
mode. The hardware reset initiates the Special Fucntion  
Register. In the Power Down mode, VCC may be lowered  
to minimize circuit power consumption. Care must be  
taken to ensure the voltage is not reduced until the power  
down mode is entered, and that the voltage is restored  
before the hardware reset is applied which freezes the  
oscillator. Reset should not be released until the oscillator  
has restarted and stabilized.  
The flag bits GF0 and GF1 may be used to determine  
whether the interrupt was received during normal  
execution or during the Idle mode. For example, the  
instruction that writes to PCON.0 can also set or clear one  
or both flag bits. When Idle mode is terminated by an  
enabled interrupt, the service routine can examine the  
status of the flag bits.  
Table 1 describes the status of the external pins while in  
The second way of terminating the Idle mode is with a  
hardware reset. Since the oscillator is still running, the the power down mode. It should be noted that if the power  
hardware reset needs to be active for only 2 machine down mode is activated while in external program  
cycles (24 oscillator periods) to complete the reset memory, the port data that is held in the Special Function  
Register P2 is restored to Port 2. If the data is a 1, the port  
pin is held high during the power down mode by the  
strong pullup, T1, shown in Figure 4.  
operation.  
Table 1 : Status of the external pins during idle and power down modes.  
MODE  
Idle  
PROGRAM MEMORY  
ALE  
PSEN  
PORT0  
Port Data  
Floating  
Port Data  
Floating  
PORT1  
Port Data  
Port Data  
Port Data  
Port Data  
PORT2  
Port Data  
Address  
PORT3  
Port Data  
Port Data  
Port Data  
Port Data  
Internal  
External  
Internal  
External  
1
1
0
0
1
1
0
0
Idle  
Power Down  
Power Down  
Port Data  
Port Data  
Figure 4. I/O Buffers in the 80C52 (Ports 1, 2, 3).  
Stop Clock Mode  
Due to static design, the MHS 80C32/C52 clock speed  
can be reduced until 0 MHz without any data loss in  
memory or registers. This mode allows step by step  
utilization, and permits to reduce system power  
consumption by bringing the clock frequency down to  
any value. At 0 MHz, the power consumption is the same  
as in the Power Down Mode.  
I/O Ports  
The I/O buffers for Ports 1, 2 and 3 are implemented as  
shown in figure 4.  
6
Rev. E (31/08/95)  

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