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74VHCT03A_04 PDF预览

74VHCT03A_04

更新时间: 2024-09-13 05:05:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
11页 226K
描述
QUAD 2-INPUT OPEN DRAIN NAND GATE

74VHCT03A_04 数据手册

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74VHCT03A  
QUAD 2-INPUT OPEN DRAIN NAND GATE  
HIGH SPEED: t = 3.9 ns (TYP.) at V = 5V  
PZ CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUTS  
OPERATING VOLTAGE RANGE:  
SOP  
TSSOP  
V
(OPR) = 4.5V to 5.5V  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 03  
IMPROVED LATCH-UP IMMUNITY  
Table 1: Order Codes  
PACKAGE  
T & R  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
SOP  
74VHCT03AMTR  
74VHCT03ATTR  
TSSOP  
DESCRIPTION  
The 74VHCT03A is an advanced high-speed  
CMOS QUAD 2-INPUT OPEN DRAIN NAND  
GATE fabricated with sub-micron silicon gate and  
regard to the supply voltage. This device can be  
used to interface 5V to 3V since all inputs are  
equipped with TTL threshold.  
2
double-layer metal wiring C MOS technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
This device can, with an external pull-up resistor,  
be used in wired AND configuration. This device  
can also be used as a led driver and in any other  
application requiring a current sink.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 3  
1/11  
December 2004  

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