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74VHC157SJ PDF预览

74VHC157SJ

更新时间: 2024-11-19 22:34:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 73K
描述
Quad 2-Input Multiplexer

74VHC157SJ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.35系列:AHC/VHC
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.1 mm负载电容(CL):50 pF
逻辑集成电路类型:MULTIPLEXER最大I(ol):0.008 A
湿度敏感等级:1功能数量:4
输入次数:2输出次数:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74VHC157SJ 数据手册

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November 1992  
Revised April 1999  
74VHC157  
Quad 2-Input Multiplexer  
age. This device can be used to interface 5V to 3V systems  
and on two supply systems such as battery back up. This  
circuit prevents device destruction due to mismatched sup-  
ply and input voltages.  
General Description  
The VHC157 is an advanced high speed CMOS Quad 2-  
Channel Multiplexer fabricated with silicon gate CMOS  
technology. It achieves the high speed operation similar to  
equivalent Bipolar Schottky TTL while maintaining the  
CMOS low power dissipation.  
Features  
High Speed: tPD = 4.1 ns (typ) at VCC = 5V  
Low power dissipation: ICC = 4 µA (max.) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min.)  
It consists of four 2-input digital multiplexers with common  
select and enable inputs. When the ENABLE input is held  
“H” level, selection of data is inhibited and all the outputs  
become “L” level. The SELECT decoding determines  
whether the I0x or I1x inputs get routed to their correspond-  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.8V (max.)  
ing outputs.  
An Input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
Pin and function compatible with 74HC157  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC157M  
74VHC157SJ  
74VHC157MTC  
74VHC157N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
I0a–I0d  
I1a–I1d  
E
Description  
Source 0 Data Inputs  
Source 1 Data Inputs  
Enable Input  
S
Select Input  
Za–Zd  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011536.prf  
www.fairchildsemi.com  

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