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74VHC157SJX PDF预览

74VHC157SJX

更新时间: 2024-09-27 22:41:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 复用器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 73K
描述
Quad 2-Input Multiplexer

74VHC157SJX 数据手册

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November 1992  
Revised April 1999  
74VHC157  
Quad 2-Input Multiplexer  
age. This device can be used to interface 5V to 3V systems  
and on two supply systems such as battery back up. This  
circuit prevents device destruction due to mismatched sup-  
ply and input voltages.  
General Description  
The VHC157 is an advanced high speed CMOS Quad 2-  
Channel Multiplexer fabricated with silicon gate CMOS  
technology. It achieves the high speed operation similar to  
equivalent Bipolar Schottky TTL while maintaining the  
CMOS low power dissipation.  
Features  
High Speed: tPD = 4.1 ns (typ) at VCC = 5V  
Low power dissipation: ICC = 4 µA (max.) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min.)  
It consists of four 2-input digital multiplexers with common  
select and enable inputs. When the ENABLE input is held  
“H” level, selection of data is inhibited and all the outputs  
become “L” level. The SELECT decoding determines  
whether the I0x or I1x inputs get routed to their correspond-  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.8V (max.)  
ing outputs.  
An Input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
Pin and function compatible with 74HC157  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC157M  
74VHC157SJ  
74VHC157MTC  
74VHC157N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
I0a–I0d  
I1a–I1d  
E
Description  
Source 0 Data Inputs  
Source 1 Data Inputs  
Enable Input  
S
Select Input  
Za–Zd  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011536.prf  
www.fairchildsemi.com  

74VHC157SJX 替代型号

型号 品牌 替代类型 描述 数据表
74AC157SJX FAIRCHILD

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