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74VHC16245TTR PDF预览

74VHC16245TTR

更新时间: 2024-11-15 21:55:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 252K
描述
16-BIT BUS TRANSCEIVER

74VHC16245TTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:AHC/VHC
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.008 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5.5 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):13.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:6.1 mmBase Number Matches:1

74VHC16245TTR 数据手册

 浏览型号74VHC16245TTR的Datasheet PDF文件第2页浏览型号74VHC16245TTR的Datasheet PDF文件第3页浏览型号74VHC16245TTR的Datasheet PDF文件第4页浏览型号74VHC16245TTR的Datasheet PDF文件第5页浏览型号74VHC16245TTR的Datasheet PDF文件第6页浏览型号74VHC16245TTR的Datasheet PDF文件第7页 
74VHC16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 4.0 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY  
=V = 28% VCC (MIN.)  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
V
NIH  
NIL  
TSSOP  
TUBE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
TSSOP  
74VHC16245TTR  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V = 0.9V (MAX.)  
PIN CONNECTION  
OLP  
DESCRIPTION  
The 74VHC16245 is an advanced high-speed  
CMOS 16-BIT BUS TRANSCEIVER (3-STATE)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
This IC is intended for two-way asynchronous  
communication between data busses; the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the busses are  
effectively isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
All floating bus terminals during High Z State must  
be held HIGH or LOW.  
July 2003  
1/10  

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