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74LVX573M PDF预览

74LVX573M

更新时间: 2024-11-14 04:47:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器逻辑集成电路光电二极管输入元件驱动
页数 文件大小 规格书
13页 303K
描述
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS

74LVX573M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.38
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:14.5 ns传播延迟(tpd):22 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74LVX573M 数据手册

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74LVX573  
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH  
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS  
HIGH SPEED:  
=6.4ns (TYP.) at V = 3.3V  
t
PD  
CC  
5V TOLERANT INPUTS  
POWER-DOWN PROTECTION ON INPUTS  
INPUT VOLTAGE LEVEL:  
V
= 0.8V, V = 2V at V =3V  
IL  
IH CC  
SOP  
TSSOP  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V =3.3V  
Table 1: Order Codes  
PACKAGE  
V
OLP  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4 mA (MIN) at V = 3V  
T & R  
OH  
OL  
CC  
SOP  
74LVX573MTR  
74LVX573TTR  
BALANCED PROPAGATION DELAYS:  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
When the LE is taken low, the Q outputs will be  
latched precisely at the logic level of D input data.  
While the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage.  
This device can be used to interface 5V to 3V. It  
combines high speed performance with the true  
CMOS low power consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVX573 is a low voltage CMOS OCTAL  
D-TYPE LATCH with 3 STATE OUTPUT NON  
INVERTING fabricated with sub-micron silicon  
gate and double-layer metal wiring C MOS  
technology. It is ideal for low power, battery  
operated and low noise 3.3V applications.  
This 8 bit D-Type latch is controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely.  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/13  
August 2004  

74LVX573M 替代型号

型号 品牌 替代类型 描述 数据表
74LVX573MTR STMICROELECTRONICS

完全替代

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS
TC74LVX573FW(ELP) TOSHIBA

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