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74LVX00SJX PDF预览

74LVX00SJX

更新时间: 2024-11-25 23:24:31
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 66K
描述
Quad 2-input NAND Gate

74LVX00SJX 数据手册

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February 1993  
Revised March 1999  
74LVX00  
Low Voltage Quad 2-Input NAND Gate  
General Description  
The LVX00 contains four 2-input NAND gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX00M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVX00SJ  
74LVX00MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
Description  
Inputs  
On  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011551.prf  
www.fairchildsemi.com  

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