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74LVX03 PDF预览

74LVX03

更新时间: 2024-11-26 04:28:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
11页 240K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE (OPEN DRAIN) WITH 5V TOLERANT INPUTS

74LVX03 数据手册

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74LVX03  
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE  
(OPEN DRAIN) WITH 5V TOLERANT INPUTS  
HIGH SPEED:  
= 4.8ns (TYP.) at V = 3.3V  
t
PD  
CC  
5V TOLERANT INPUTS  
INPUT VOLTAGE LEVEL:  
V =0.8V, V =2V at V =3V  
IL  
IH  
CC  
LOW POWER DISSIPATION:  
= 2 µA (MAX.) at T =25°C  
SOP  
TSSOP  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
CC  
T & R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 03  
IMPROVED LATCH-UP IMMUNITY  
POWER DOWN PROTECTION ON INPUTS  
SOP  
74LVX03MTR  
74LVX03TTR  
TSSOP  
can also be used as a led driver and in any other  
application requiring a current sink.  
DESCRIPTION  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage.  
This device can be used to interface 5V to 3V  
system. It combines high speed performance with  
the true CMOS low power consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74LVX03 is a low voltage CMOS OPEN  
DRAIN HEX INVERTER fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C MOS technology. It is ideal for low  
power, battery operated and low noise 3.3V  
applications.  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
This device can, with an external pull-up resistor,  
be used in wired AND configuration. This device  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 2  
1/11  
August 2004  

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