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74LVX02T PDF预览

74LVX02T

更新时间: 2024-11-10 23:24:31
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 58K
描述
Quad 2-input NOR Gate

74LVX02T 数据手册

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74LVX02  
LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE  
HIGH SPEED:tPD =4.5ns (TYP.) atVCC = 3.3V  
INPUT VOLTAGELEVEL:  
VIL =0.8V,VIH =2V atVCC =3V  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
M
T
LOWNOISE:  
(Micro Package)  
(TSSOPPackage)  
VOLP =0.3 V (TYP.)at VCC = 3.3V  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 4 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
ORDER CODES :  
74LVX02M  
74LVX02T  
including buffer output, which enable high noise  
immunity and stable output.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consumption.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES02  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVX02 is a low voltage CMOS QUAD  
2-INPUT NOR GATE fabricated with sub-micron  
silicon gate and double-layermetal wiring C2MOS  
technology.It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 3 stages  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
March 1999  

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