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74LVX02M PDF预览

74LVX02M

更新时间: 2024-11-26 04:28:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
11页 158K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE WITH 5V TOLERANT INPUTS

74LVX02M 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.36
Is Samacsys:N系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):19 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74LVX02M 数据手册

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74LVX02  
LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE  
WITH 5V TOLERANT INPUTS  
HIGH SPEED:  
= 4.5ns (TYP.) at V = 3.3V  
t
PD  
CC  
5V TOLERANT INPUTS  
INPUT VOLTAGE LEVEL:  
V =0.8V, V =2V at V =3V  
IL  
IH  
CC  
LOW POWER DISSIPATION:  
= 2 µA (MAX.) at T =25°C  
SOP  
TSSOP  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
V
Table 1: Order Codes  
PACKAGE  
OLP  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
T & R  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVX02MTR  
74LVX02TTR  
t
t
PLH  
PHL  
TSSOP  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
CC  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage.  
This device can be used to interface 5V to 3V  
system. It combines high speed performance with  
the true CMOS low power consumption. All inputs  
and outputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD  
immunity and transient excess voltage.  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 02  
IMPROVED LATCH-UP IMMUNITY  
POWER DOWN PROTECTION ON INPUTS  
DESCRIPTION  
The 74LVX02 is a low voltage CMOS QUAD  
2-INPUT NOR GATE fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power, battery  
operated and low noise 3.3V applications.  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
August 2004  

74LVX02M 替代型号

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