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74LVX02MSCX PDF预览

74LVX02MSCX

更新时间: 2024-11-23 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
6页 88K
描述
NOR Gate, LV/LV-A/LVX/H Series, 4-Func, 2-Input, CMOS, PDSO14, EIAJ TYPE1, PLASTIC, SSOP-14

74LVX02MSCX 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:LSSOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
其他特性:INPUTS CAN BE DRIVEN BY 3V OR 5V COMPONENTS系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14长度:5 mm
逻辑集成电路类型:NOR GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
传播延迟(tpd):8 ns认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LVX02MSCX 数据手册

 浏览型号74LVX02MSCX的Datasheet PDF文件第2页浏览型号74LVX02MSCX的Datasheet PDF文件第3页浏览型号74LVX02MSCX的Datasheet PDF文件第4页浏览型号74LVX02MSCX的Datasheet PDF文件第5页浏览型号74LVX02MSCX的Datasheet PDF文件第6页 
May 1993  
Revised February 2005  
74LVX02  
Low Voltage Quad 2-Input NOR Gate  
General Description  
The LVX02 contains four 2-input NOR gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code  
Package  
Order Number  
Package Description  
Number  
74LVX02M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX02SJ  
74LVX02MTC  
MTC14  
MTC14  
74LVX02MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
On  
Description  
Inputs  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS011600  
www.fairchildsemi.com  

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