Datasheet > 74LVT16501ADL,112

74LVT16501ADL,112

更新时间： 2024-11-17 14:21:51

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
19页	96K
描述
74LVT16501A - 3.3 V LVT 18-bit universal bus transceiver; 3-state SSOP 56-Pin

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

74LVT16501ADL,112 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	生命周期：	Transferred
零件包装代码：	SSOP	包装说明：	7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
针数：	56	Reach Compliance Code：	unknown
风险等级：	5.7	Base Number Matches：	1

74LVT16501ADL,112 数据手册

浏览型号74LVT16501ADL,112的Datasheet PDF文件第2页

浏览型号74LVT16501ADL,112的Datasheet PDF文件第3页

浏览型号74LVT16501ADL,112的Datasheet PDF文件第4页

浏览型号74LVT16501ADL,112的Datasheet PDF文件第5页

浏览型号74LVT16501ADL,112的Datasheet PDF文件第6页

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

Rev. 04 — 19 May 2006

Product data sheet

1. General description

The 74LVT16501A is a high-performance BiCMOS product designed for V_CCoperation at

3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions.

Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable

(LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.

If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the LOW-to-HIGH

transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the

outputs are in the high-impedance state.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

Active bus hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

2. Features

I 18-bit bidirectional bus interface

I 3-state buffers

I Output capability: +64 mA to −32 mA

I TTL input and output switching levels

I Input and output interface capability to systems at 5 V supply

I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

I Live insertion and extraction permitted

I Power-up reset

I Power-up 3-state

I No bus current loading when output is tied to 5 V bus

I Positive-edge triggered clock inputs

I Latch-up protection:

N JESD78: exceeds 500 mA

I ESD protection:

N MIL STD 883, method 3015: exceeds 2000 V

N Machine model: exceeds 200 V

12 3 4 5 6 7...19

中文翻译

下载PDF

与74LVT16501ADL,112相关器件

型号	品牌	获取价格	描述	数据表
74LVT16501ADL,512	NXP	获取价格	74LVT16501A - 3.3 V LVT 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74LVT16501ADL,518	NXP	获取价格	74LVT16501A - 3.3 V LVT 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74LVT16501ADL-T	ETC	获取价格	18-Bit Bus Transceiver
74LVT16501DGGRE4	TI	获取价格	3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
74LVT16541	NXP	获取价格	3.3V ABT 16-bit buffer/driver 3-State
74LVT16541A	NXP	获取价格	3.3V ABT 16-bit buffer/driver 3-State
74LVT16541ADGG	NXP	获取价格	3.3V ABT 16-bit buffer/driver 3-State
74LVT16541ADL	NXP	获取价格	3.3V ABT 16-bit buffer/driver 3-State
74LVT16541ADL-T	NXP	获取价格	IC LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, SSOP3-48, Bus Driver/Trans
74LVT16543	NXP	获取价格	3.3V LVT 16-bit registered transceiver 3-State

与74LVT16501ADL,112相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVT16501ADL,112

74LVT16501ADL,112 技术参数

74LVT16501ADL,112 数据手册

与74LVT16501ADL,112相关器件

与74LVT16501ADL,112相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVT16501ADL,112

74LVT16501ADL,112 技术参数

74LVT16501ADL,112 数据手册

与74LVT16501ADL,112相关器件

与74LVT16501ADL,112相关文章

您还可以找

您在本页遇到什么问题？