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74LVT16543MTDX PDF预览

74LVT16543MTDX

更新时间: 2024-11-04 23:24:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
8页 79K
描述
Dual 8-bit Bus Transceiver

74LVT16543MTDX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:unknown
风险等级:5.21其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVTJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.064 A
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):5.8 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:6.1 mm
Base Number Matches:1

74LVT16543MTDX 数据手册

 浏览型号74LVT16543MTDX的Datasheet PDF文件第2页浏览型号74LVT16543MTDX的Datasheet PDF文件第3页浏览型号74LVT16543MTDX的Datasheet PDF文件第4页浏览型号74LVT16543MTDX的Datasheet PDF文件第5页浏览型号74LVT16543MTDX的Datasheet PDF文件第6页浏览型号74LVT16543MTDX的Datasheet PDF文件第7页 
January 2000  
Revised October 2001  
74LVT16543 74LVTH16543  
Low Voltage 16-Bit Registered Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT16543 and LVTH16543 16-bit transceivers  
contain two sets of D-type latches for temporary storage of  
data flowing in either direction. Separate Latch Enable and  
Output Enable inputs are provided for each register to per-  
mit independent control of inputting and outputting in either  
direction of data flow. Each byte has separate control  
inputs, which can be shorted together for full 16-bit opera-  
tion.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16543)  
Also available without bushold feature (74LVT16543)  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH16543 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Outputs source/sink 32 mA/+64 mA  
Functionally compatible with the 74 series 16543  
Latch-up conforms to JEDEC JED78  
ESD performance:  
These transceivers are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
interface to  
a 5V environment. The LVT16543 and  
Human-body model > 2000V  
LVTH16543 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining low power dissipation.  
Machine model > 200V  
Charged-device model > 1000V  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT16543MEA  
(Preliminary)  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16543MTD  
(Preliminary)  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16543MEA  
74LVTH16543MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2001 Fairchild Semiconductor Corporation  
DS012449  
www.fairchildsemi.com  

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