5秒后页面跳转
74LVC32APW-Q100 PDF预览

74LVC32APW-Q100

更新时间: 2024-01-19 15:51:19
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
13页 224K
描述
Quad 2-input OR gate

74LVC32APW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP,
针数:14Reach Compliance Code:compliant
风险等级:5.37系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14长度:5 mm
逻辑集成电路类型:OR GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):10.4 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74LVC32APW-Q100 数据手册

 浏览型号74LVC32APW-Q100的Datasheet PDF文件第2页浏览型号74LVC32APW-Q100的Datasheet PDF文件第3页浏览型号74LVC32APW-Q100的Datasheet PDF文件第4页浏览型号74LVC32APW-Q100的Datasheet PDF文件第5页浏览型号74LVC32APW-Q100的Datasheet PDF文件第6页浏览型号74LVC32APW-Q100的Datasheet PDF文件第7页 
74LVC32A-Q100  
Quad 2-input OR gate  
Rev. 3 — 12 September 2018  
Product data sheet  
1. General description  
The 74LVC32A-Q100 provides four 2-input OR gates.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V applications.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
5 V tolerant inputs for interlacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Multiple package options  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC32AD-Q100  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74LVC32APW-Q100 -40 °C to +125 °C  
74LVC32ABQ-Q100 -40 °C to +125 °C  
TSSOP14  
plastic thin shrink small outline package; 14 leads; SOT402-1  
body width 4.4 mm  
DHVQFN14 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 14 terminals;  
body 2.5 × 3 × 0.85 mm  
SOT762-1  
 
 
 

与74LVC32APW-Q100相关器件

型号 品牌 获取价格 描述 数据表
74LVC32APW-T NXP

获取价格

IC LVC/LCX/Z SERIES, QUAD 2-INPUT OR GATE, PDSO14, Gate
74LVC32A-Q100 NEXPERIA

获取价格

Quad 2-input OR gate
74LVC32ATS DIODES

获取价格

QUADRUPLE 2-INPUT OR GATES
74LVC32ATS-13 DIODES

获取价格

QUADRUPLE 2-INPUT OR GATES
74LVC32ATTR STMICROELECTRONICS

获取价格

LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE HIGH PERFORMANCE
74LVC32D-T NXP

获取价格

暂无描述
74LVC332BQ NXP

获取价格

LVC/LCX/Z SERIES, TRIPLE 3-INPUT OR GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO
74LVC332D NXP

获取价格

LVC/LCX/Z SERIES, TRIPLE 3-INPUT OR GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-
74LVC332DB NXP

获取价格

LVC/LCX/Z SERIES, TRIPLE 3-INPUT OR GATE, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP
74LVC332PW NXP

获取价格

LVC/LCX/Z SERIES, TRIPLE 3-INPUT OR GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSO