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74LVC240AD PDF预览

74LVC240AD

更新时间: 2024-12-01 11:10:23
品牌 Logo 应用领域
安世 - NEXPERIA PC驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 251K
描述
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-stateProduction

74LVC240AD 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.56
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:1737Samacsys Pin Count:20
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOT163-1Samacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):14.6 ns座面最大高度:2.65 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74LVC240AD 数据手册

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74LVC240A  
Octal buffer/line driver with 5 V tolerant inputs/outputs;  
inverting; 3-state  
Rev. 9 — 6 May 2021  
Product data sheet  
1. General description  
The 74LVC240A is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be  
used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and  
2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume  
a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature  
allows the use of these devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Overvoltage tolerant inputs to 5.5 V  
Wide supply voltage range from 1.2 to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
IOFF circuitry provides partial Power-down mode operation  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC240AD  
-40 °C to +125 °C  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74LVC240APW -40 °C to +125 °C  
74LVC240ABQ -40 °C to +125 °C  
TSSOP20  
plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
SOT764-1  
DHVQFN20 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 20 terminals;  
body 2.5 × 4.5 × 0.85 mm  
 
 
 

74LVC240AD 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC240ADWR TI

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