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74LVC240APW-T PDF预览

74LVC240APW-T

更新时间: 2024-11-30 20:32:03
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 210K
描述
IC LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20, Bus Driver/Transceiver

74LVC240APW-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.07Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):7.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74LVC240APW-T 数据手册

 浏览型号74LVC240APW-T的Datasheet PDF文件第2页浏览型号74LVC240APW-T的Datasheet PDF文件第3页浏览型号74LVC240APW-T的Datasheet PDF文件第4页浏览型号74LVC240APW-T的Datasheet PDF文件第5页浏览型号74LVC240APW-T的Datasheet PDF文件第6页浏览型号74LVC240APW-T的Datasheet PDF文件第7页 
74LVC240A  
Octal buffer/line driver with 5 V tolerant inputs/outputs;  
inverting; 3-state  
Rev. 8 — 29 November 2011  
Product data sheet  
1. General description  
The 74LVC240A is an octal inverting buffer/line driver with 3-state outputs. The 3-state  
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes  
the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs  
makes the circuit highly tolerant of slower input rise and fall times.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices as translators in  
mixed 3.3 V or 5 V applications.  
The 74LVC240A is functionally identical to the 74LVC244A except that the 244 has  
non-inverting outputs.  
2. Features and benefits  
5 V tolerant inputs for interlacing with 5 V logic  
Supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
High-impedance when VCC = 0 V  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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