Datasheet > 74LVC1G125

74LVC1G125

更新时间： 2024-09-14 22:56:19

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
8页	122K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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74LVC1G125 数据手册

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

DBV OR DCK PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Feature Supports Partial-Power-Down

off

GND

Mode Operation

Supports 5-V V

Operation

Package Options Include Plastic

Small-Outline Transistor (DBV, DCK)

Packages

description

This bus buffer gate is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the

output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,

off

preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G125 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

†

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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