Datasheet > 74LVC1G04GN

74LVC1G04GN

更新时间： 2024-11-10 04:05:11

品牌	Logo	应用领域
恩智浦 - NXP		输入元件光电二极管
页数	文件大小	规格书
19页	347K
描述
LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6

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74LVC1G04GN 数据手册

74LVC1G04

Single inverter

Rev. 11 — 12 April 2012

Product data sheet

1. General description

The 74LVC1G04 provides one inverting buffer.

Input can be driven from either 3.3 V or 5 V devices. These features allow the use of

these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant inputs for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C.

12 3 4 5 6 7...19

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