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74LVC1G04GW,132 PDF预览

74LVC1G04GW,132

更新时间: 2024-11-09 20:06:31
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
19页 347K
描述
Inverter, LVC/LCX/Z Series, 1-Func, 1-Input, CMOS, PDSO5

74LVC1G04GW,132 技术参数

生命周期:Active包装说明:TSSOP,
Reach Compliance Code:unknown风险等级:5.57
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G5
长度:2.05 mm逻辑集成电路类型:INVERTER
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):9.5 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mmBase Number Matches:1

74LVC1G04GW,132 数据手册

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74LVC1G04  
Single inverter  
Rev. 11 — 12 April 2012  
Product data sheet  
1. General description  
The 74LVC1G04 provides one inverting buffer.  
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of  
these devices in a mixed 3.3 V and 5 V environment.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C.  

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