Datasheet > 74LVC14APW118

74LVC14APW118

更新时间： 2024-11-17 11:50:19

品牌	Logo	应用领域
恩智浦 - NXP		触发器
页数	文件大小	规格书
26页	137K
描述
Hex inverting Schmitt trigger with 5 V tolerant input

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LVC14APW118 数据手册

74LVC1G99

Ultra-conﬁgurable multiple function gate; 3-state

Rev. 01 — 3 January 2008

Product data sheet

1. General description

The 74LVC1G99 provides a low voltage, ultra-conﬁgurable, multiple function gate with

3-state output. The device can be conﬁgured as one of several logic functions including,

AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components

are required to conﬁgure the device as all inputs can be connected directly to V_CCor GND.

The 3-state output is controlled by the output enable input (OE). A HIGH level at OE

causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the

output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and

D).

Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input

signals, transforming them into sharply deﬁned, jitter free output signals. By eliminating

leakage current paths to V_CCand GND, the inputs and disabled output are also

over-voltage tolerant, making the device suitable for mixed-voltage applications.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74LVC1G99 is fully speciﬁed over the supply range from 1.65 V to 5.5 V.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...26

中文翻译

下载PDF

与74LVC14APW118相关器件

型号	品牌	获取价格	描述	数据表
74LVC14APWDH	NXP	获取价格	Hex inverting Schmitt-trigger with 5V tolerant input
74LVC14APWDH-T	NXP	获取价格	IC LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14, Gate
74LVC14APW-Q100	NXP	获取价格	LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSS
74LVC14APW-Q100	NEXPERIA	获取价格	Hex inverting Schmitt trigger with 5 V tolerant input
74LVC14APW-T	NXP	获取价格	Hex inverting Schmitt trigger with 5 V tolerant input
74LVC14APW-T118	NXP	获取价格	LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
74LVC14A-Q100	NEXPERIA	获取价格	Hex inverting Schmitt trigger with 5 V tolerant input
74LVC14AS14	DIODES	获取价格	HEX INVERTERS WITH SCHMITT TRIGGER INPUTS
74LVC14AS14-13	DIODES	获取价格	HEX INVERTERS WITH SCHMITT TRIGGER INPUTS
74LVC14AT14	DIODES	获取价格	HEX INVERTERS WITH SCHMITT TRIGGER INPUTS