Datasheet > 逻辑 > 栅极> 74LVC14APW-T

74LVC14APW-T

更新时间： 2024-02-12 06:25:41

品牌	Logo	应用领域
恩智浦 - NXP		栅极触发器逻辑集成电路光电二极管
页数	文件大小	规格书
26页	137K
描述
Hex inverting Schmitt trigger with 5 V tolerant input

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74LVC14APW-T 技术参数

生命周期：	Obsolete	包装说明：	SSOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.25	系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-G14	长度：	6.2 mm
负载电容（CL）：	50 pF	逻辑集成电路类型：	INVERTER
功能数量：	6	输入次数：	1
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	传播延迟（tpd）：	7.3 ns
认证状态：	Not Qualified	座面最大高度：	2 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	1.2 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	5.3 mm
Base Number Matches：	1

74LVC14APW-T 数据手册

74LVC1G99

Ultra-conﬁgurable multiple function gate; 3-state

Rev. 01 — 3 January 2008

Product data sheet

1. General description

The 74LVC1G99 provides a low voltage, ultra-conﬁgurable, multiple function gate with

3-state output. The device can be conﬁgured as one of several logic functions including,

AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components

are required to conﬁgure the device as all inputs can be connected directly to V_CCor GND.

The 3-state output is controlled by the output enable input (OE). A HIGH level at OE

causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the

output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and

D).

Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input

signals, transforming them into sharply deﬁned, jitter free output signals. By eliminating

leakage current paths to V_CCand GND, the inputs and disabled output are also

over-voltage tolerant, making the device suitable for mixed-voltage applications.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74LVC1G99 is fully speciﬁed over the supply range from 1.65 V to 5.5 V.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...26

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