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74LS193DCQM PDF预览

74LS193DCQM

更新时间: 2024-11-18 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器时钟
页数 文件大小 规格书
7页 77K
描述
Binary Counter, Synchronous, Bidirectional, TTL, CDIP16,

74LS193DCQM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP16,.3
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.32计数方向:BIDIRECTIONAL
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified子类别:Counters
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

74LS193DCQM 数据手册

 浏览型号74LS193DCQM的Datasheet PDF文件第2页浏览型号74LS193DCQM的Datasheet PDF文件第3页浏览型号74LS193DCQM的Datasheet PDF文件第4页浏览型号74LS193DCQM的Datasheet PDF文件第5页浏览型号74LS193DCQM的Datasheet PDF文件第6页浏览型号74LS193DCQM的Datasheet PDF文件第7页 
September 1986  
Revised March 2000  
DM74LS193  
Synchronous 4-Bit Binary Counter with Dual Clock  
of the count and load inputs. The clear, count, and load  
inputs are buffered to lower the drive requirements of clock  
drivers, etc., required for long words.  
General Description  
The DM74LS193 circuit is a synchronous up/down 4-bit  
binary counter. Synchronous operation is provided by hav-  
These counters were designed to be cascaded without the  
ing all flip-flops clocked simultaneously, so that the outputs  
need for external circuitry. Both borrow and carry outputs  
change together when so instructed by the steering logic.  
are available to cascade both the up and down counting  
This mode of operation eliminates the output counting  
functions. The borrow output produces a pulse equal in  
spikes normally associated with asynchronous (ripple-  
width to the count down input when the counter underflows.  
clock) counters.  
Similarly, the carry output produces a pulse equal in width  
The outputs of the four master-slave flip-flops are triggered  
to the count down input when an overflow condition exists.  
by a LOW-to-HIGH level transition of either count (clock)  
The counters can then be easily cascaded by feeding the  
input. The direction of counting is determined by which  
borrow and carry outputs to the count down and count up  
count input is pulsed while the other count input is held  
inputs respectively of the succeeding counter.  
HIGH.  
The counter is fully programmable; that is, each output may  
Features  
be preset to either level by entering the desired data at the  
Fully independent clear input  
inputs while the load input is LOW. The output will change  
independently of the count pulses. This feature allows the  
counters to be used as modulo-N dividers by simply modi-  
fying the count length with the preset inputs.  
Synchronous operation  
Cascading circuitry provided internally  
Individual preset each flip-flop  
A clear input has been provided which, when taken to a  
high level, forces all outputs to the low level; independent  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS193M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
DM74LS193N  
N16E  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006406  
www.fairchildsemi.com  

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