74LCX245

更新时间： 2024-11-18 22:45:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		总线收发器输出元件输入元件
页数	文件大小	规格书
13页	282K
描述
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

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74LCX245 数据手册

74LCX245

LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER

(3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

■

5V TOLERANT INPUTS AND OUTPUTS

HIGH SPEED:

= 7.0 ns (MAX.) at V = 3V

■

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

|I | = I = 24mA (MIN) at V = 3V

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

PLH

PHL

■

OPERATING VOLTAGE RANGE:

(OPR) = 2.0V to 3.6V (1.5V Data

T & R

SOP

74LCX245MTR

74LCX245TTR

Retention)

TSSOP

■

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 245

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

ESD PERFORMANCE:

This IC is intended for two way asynchronous

communication between data buses; the direction

of data transmission is determined by DIR input.

The enable input G can be used to disable the

device so that the buses are effectively isolated.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LCX245 is a low voltage CMOS OCTAL

BUS TRANSCEIVER (3-STATE) fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology. It is ideal for low power

and high speed 3.3V applications; it can be

interfaced to 5V signal environment for both inputs

and outputs.

All floating bus terminals during High Z state must

be held HIGH or LOW.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/13

September 2004

12 3 4 5 6 7...13

中文翻译

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