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74LCX245M PDF预览

74LCX245M

更新时间: 2024-11-18 23:24:19
品牌 Logo 应用领域
其他 - ETC 总线收发器
页数 文件大小 规格书
10页 71K
描述
Single 8-bit Bus Transceiver

74LCX245M 数据手册

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74LCX245  
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(3-STATE)  
WITH 5V TOLERAT INPUTS AND OUTPUTS  
5V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED :  
t
= 7.0 ns (MAX.) at V = 3V  
PD  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN) at V = 3V  
SOP  
TSSOP  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
t
t
PHL  
ORDER CODES  
PACKAGE  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.0V to 3.6V (1.5V Data  
TUBE  
T & R  
V
CC  
SOP  
74LCX245M  
74LCX245MTR  
74LCX245TTR  
Retention)  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 245  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
It has same speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
This IC is intended for two way asynchronous  
communication between data buses; the direction  
of data transmission is determined by DIR input.  
The enable input G can be used to disable the  
device so that the buses are effectively isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LCX245 is a low voltage CMOS OCTAL  
BUS TRANSCEIVER (3-STATE) fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology. It is ideal for low power  
and high speed 3.3V applications; it can be  
interfaced to 5V signal environment for both inputs  
and outputs.  
All floating bus terminals during High Z state must  
be held HIGH or LOW.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/10  

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