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74HCT4094D,118 PDF预览

74HCT4094D,118

更新时间: 2024-01-01 17:36:33
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 66K
描述
74HC(T)4094 - 8-stage shift-and-store bus register SOP 16-Pin

74HCT4094D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:MINI, PLASTIC, SO-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.02
其他特性:PARALLEL OUTPUT IS LATCHED; UNLATCHED SERIAL SHIFT RIGHT OUTPUT计数方向:RIGHT
系列:HCTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:20000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):65 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:20 MHz
Base Number Matches:1

74HCT4094D,118 数据手册

 浏览型号74HCT4094D,118的Datasheet PDF文件第4页浏览型号74HCT4094D,118的Datasheet PDF文件第5页浏览型号74HCT4094D,118的Datasheet PDF文件第6页浏览型号74HCT4094D,118的Datasheet PDF文件第7页浏览型号74HCT4094D,118的Datasheet PDF文件第8页浏览型号74HCT4094D,118的Datasheet PDF文件第9页 
Philips Semiconductors  
Product specification  
8-stage shift-and-store bus register  
74HC/HCT4094  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.8 Waveforms showing the strobe (STR) to  
output (QPn) propagation delays and the  
strobe pulse width and the clock set-up and  
hold times for the strobe input.  
Fig.7 Waveforms showing the clock (CP) to  
output (QPn, QS1, QS2) propagation  
delays, the clock pulse width and the  
maximum clock frequency.  
The shaded areas indicate when the input is  
permitted to change for predictable output  
performance.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.10 Waveforms showing the data set-up and  
hold times for the data input (D).  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.9 Waveforms showing the 3-state enable and  
disable times for input OE.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
10  

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