Datasheet > 74HCT4075D

74HCT4075D

更新时间： 2024-11-10 11:14:55

品牌	Logo	应用领域
安世 - NEXPERIA		栅光电二极管逻辑集成电路触发器
页数	文件大小	规格书
11页	211K
描述
Triple 3-input OR gateProduction

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74HCT4075D 数据手册

74HC4075; 74HCT4075

Triple 3-input OR gate

Rev. 5 — 20 June 2023

Product data sheet

1. General description

The 74HC4075; 74HCT4075 is a triple 3-input OR gate. Inputs include clamp diodes. This enables

the use of current limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

Complies with JEDEC standard no. 7A

Input levels:

For 74HC4075: CMOS level

For 74HCT4075: TTL level

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC4075D

74HCT4075D

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

4. Functional diagram

≥1

aaa-024793

aaa-024794

aaa-024795

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

12 3 4 5 6 7...11

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