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Datasheet > 74HCT165PW-Q100,11
74HCT165PW-Q100,11 PDF预览

74HCT165PW-Q100,11

更新时间： 2024-11-04 15:26:35
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恩智浦 - NXP /
页数 文件大小 规格书
21页 304K
描述
74HC(T)165-Q100 - 8-bit parallel-in/serial out shift register TSSOP 16-Pin

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74HCT165PW-Q100,11 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
针数：16Reach Compliance Code：compliant
风险等级：5.77Base Number Matches：1

74HCT165PW-Q100,11 数据手册

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74HC165-Q100; 74HCT165-Q100  
8-bit parallel-in/serial out shift register  
Rev. 1 — 17 July 2012  
Product data sheet  
1. General description  
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that  
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky  
TTL (LSTTL).  
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers  
with complementary serial outputs (Q7 and Q7) available from the last stage. When the  
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the  
register asynchronously.  
When PL is HIGH, data enters the register serially at the DS input and shifts one place to  
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature  
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the  
succeeding stage.  
The clock input is a gated-OR structure which allows one input to be used as an active  
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary  
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE  
should only take place while CP HIGH for predictable operation. Either the CP or the CE  
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data  
when PL is activated.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Asynchronous 8-bit parallel load  
Synchronous serial input  
Complies with JEDEC standard no. 7A  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
3. Applications  
Parallel-to-serial data conversion  
 
 
 
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74HCT165PW-Q100,11 替代型号

型号 品牌 替代类型 描述 数据表
74HCT165BQ NXP

完全替代

 8-bit parallel-in/serial out shift register

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