Datasheet > 74HCT08AN_08

74HCT08AN_08

更新时间： 2024-11-20 12:51:03

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
10页	304K
描述
Quad 2-Input AND Gate

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74HCT08AN_08 数据手册

February 2008

74VHCT08A

Quad 2-Input AND Gate

Features

General Description

■ High speed: t = 5.0ns (typ.) at T = 25°C

The VHCT08A is an advanced high speed CMOS 2

Input AND Gate fabricated with silicon gate CMOS tech-

nology. It achieves the high-speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

■ High noise immunity: V = 2.0V, V = 0.8V

■ Power down protection is provided on all inputs and

outputs

■ Low noise: V

= 0.8V (max.)

OLP

The internal circuit is composed of 4 stages including

buffer output, which provide high noise immunity and

stable output.

■ Low power dissipation: I = 2µA (max.) @ T = 25°C

■ Pin and function compatible with 74HCT08

Protection circuits ensure that 0V to 7V can be applied to

the input pins without regard to the supply voltage and to

the output pins with V

= 0V. These circuits prevent

device destruction due to mismatched supply and input/

output voltages. This device can be used to interface 3V

to 5V systems and two supply systems such as battery

backup.

Ordering Information

Package

Order Number

Number

Package Description

74VHCT08AM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHCT08ASJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHCT08AMTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74HCT08AN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74VHCT08A Rev. 1.3.0

www.fairchildsemi.com

12 3 4 5 6 7...10

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