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74HCT08DR2G PDF预览

74HCT08DR2G

更新时间: 2024-11-24 11:52:11
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 138K
描述
Quad 2-Input AND Gate With LSTTL−Compatible Inputs High−Performance Silicon−Gate CMOS

74HCT08DR2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.01
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:22 ns
传播延迟(tpd):22 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

74HCT08DR2G 数据手册

 浏览型号74HCT08DR2G的Datasheet PDF文件第2页浏览型号74HCT08DR2G的Datasheet PDF文件第3页浏览型号74HCT08DR2G的Datasheet PDF文件第4页浏览型号74HCT08DR2G的Datasheet PDF文件第5页浏览型号74HCT08DR2G的Datasheet PDF文件第6页浏览型号74HCT08DR2G的Datasheet PDF文件第7页 
74HCT08  
Quad 2-Input AND Gate  
With LSTTLCompatible Inputs  
HighPerformance SiliconGate CMOS  
The 74HCT08 is identical in pinout to the LS08. The device has  
TTLcompatible inputs.  
http://onsemi.com  
MARKING  
Features  
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOSCompatible Input Levels  
DIAGRAMS  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
14  
SOIC14  
D SUFFIX  
CASE 751A  
HCT08G  
AWLYWW  
14  
14  
Low Input Current: 1.0 mA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 24 FETs or 6 Equivalent Gates  
These are PbFree Devices  
1
14  
HCT  
08  
TSSOP14  
DT SUFFIX  
CASE 948G  
ALYW G  
1
G
LOGIC DIAGRAM  
1
1
A1  
3
Y1  
2
B1  
HCT08 = Device Code  
4
A
= Assembly Location  
A2  
6
WL or L = Wafer Lot  
Y2  
5
Y
= Year  
B2  
WW or W = Work Week  
Y = AB  
9
G or G  
= PbFree Package  
A3  
8
Y3  
(Note: Microdot may be in either location)  
10  
B3  
12  
A4  
11  
Y4  
13  
FUNCTION TABLE  
B4  
Inputs  
Output  
Y
PIN 14 = V  
CC  
PIN 7 = GND  
A
B
Pinout: 14Lead Packages (Top View)  
L
L
L
H
L
L
L
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
H
H
L
14  
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
May, 2009 Rev. 2  
74HCT08/D  

74HCT08DR2G 替代型号

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