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74HC4051PW PDF预览

74HC4051PW

更新时间: 2024-11-13 11:11:31
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管
页数 文件大小 规格书
28页 394K
描述
8-channel analog multiplexer/demultiplexerProduction

74HC4051PW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.01
Is Samacsys:N其他特性:ALSO OPERATES ON VCC-VEE 2 V TO 10 V SUPPLY
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXERJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
湿度敏感等级:1信道数量:8
功能数量:1端子数量:16
标称断态隔离度:50 dB通态电阻匹配规范:9 Ω
最大通态电阻 (Ron):180 Ω最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):10 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
最长断开时间:87 ns最长接通时间:104 ns
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

74HC4051PW 数据手册

 浏览型号74HC4051PW的Datasheet PDF文件第2页浏览型号74HC4051PW的Datasheet PDF文件第3页浏览型号74HC4051PW的Datasheet PDF文件第4页浏览型号74HC4051PW的Datasheet PDF文件第5页浏览型号74HC4051PW的Datasheet PDF文件第6页浏览型号74HC4051PW的Datasheet PDF文件第7页 
74HC4051; 74HCT4051  
8-channel analog multiplexer/demultiplexer  
Rev. 11 — 5 December 2022  
Product data sheet  
1. General description  
The 74HC4051; 74HCT4051 is a single-pole octal-throw analog switch (SP8T) suitable for use in  
analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select  
inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a common input/output (Z) and a  
digital enable input (E). When E is HIGH, the switches are turned off. Inputs include clamp diodes.  
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide analog input voltage range from -5 V to +5 V  
CMOS low power dissipation  
High noise immunity  
Complies with JEDEC standards  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Low ON resistance:  
80 Ω (typical) at VCC - VEE = 4.5 V  
70 Ω (typical) at VCC - VEE = 6.0 V  
60 Ω (typical) at VCC - VEE = 9.0 V  
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals  
Typical ‘break before make’ built-in  
ESD protection:  
HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V  
CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Applications  
Analog multiplexing and demultiplexing  
Digital multiplexing and demultiplexing  
Signal gating  
 
 
 

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