Datasheet > 74HC4020BQ

74HC4020BQ

更新时间： 2024-12-02 11:12:59

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
16页	273K
描述
14-stage binary ripple counterProduction

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数据手册

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74HC4020BQ 数据手册

74HC4020; 74HCT4020

14-stage binary ripple counter

Rev. 8 — 7 September 2021

Product data sheet

1. General description

The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an

overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3

to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all

counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a

static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors

to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 6.0 V

•

CMOS low power dissipation

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

Input levels:

•

For 74HC4020: CMOS level

For 74HCT4020: TTL level

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Multiple package options

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

•

Frequency dividing circuits

Time delay circuits

Control counters

12 3 4 5 6 7...16

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