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74HC40105N,652 PDF预览

74HC40105N,652

更新时间： 2024-09-17 15:45:23
品牌 Logo 应用领域
恩智浦 - NXP 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
37页 350K
描述
74HC(T)40105 - 4-bit x 16-word FIFO register DIP 16-Pin

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74HC40105N,652 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.77
最长访问时间：600 ns其他特性：REGISTER BASED; BUBBLE BACK 750NS
最大时钟频率 (fCLK)：14 MHz周期时间：71.428 ns
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：21.6 mm内存密度：64 bit
内存集成电路类型：OTHER FIFO内存宽度：4
功能数量：1端子数量：16
字数：16 words字数代码：16
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：16X4
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2/6 V
认证状态：Not Qualified座面最大高度：4.7 mm
子类别：FIFOs最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：NO技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.62 mmBase Number Matches：1

74HC40105N,652 数据手册

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74HC40105; 74HCT40105  
4-bit x 16-word FIFO register  
Rev. 3 — 25 September 2013  
Product data sheet  
1. General description  
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that  
can store 16 4-bit words. It can handle input and output data at different shifting rates.  
This feature makes it particularly useful as a buffer between asynchronous systems. Each  
word position in the register is clocked by a control flip-flop, which stores a marker bit. A  
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in  
that position. The control flip-flop detects the state of the preceding flip-flop and  
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the  
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The  
clock pulse transfers data from the preceding four data latches into its own four data  
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have  
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid  
data ripples through to the output end. As a result, the status of the first control flip-flop  
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop  
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest  
data is removed from the bottom of the data stack (output end), all data entered later will  
automatically ripple toward the output. Inputs include clamp diodes that enable the use of  
current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Independent asynchronous inputs and outputs  
Expandable in either direction  
Reset capability  
Status indicators on inputs and outputs  
3-state outputs  
Input levels:  
For 74HC40105: CMOS level  
For 74HCT40105: TTL level  
3-state outputs  
Complies with JEDEC standard JESD7A  
ESD protection:  
HBM JESD22-A114F exceeds 2 000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 
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74HC40105N,652 替代型号

型号 品牌 替代类型 描述 数据表
74HCT40105N,112 NXP

类似代替

 74HC(T)40105 - 4-bit x 16-word FIFO register DIP 16-Pin
SN74ALS232BN TI

功能相似

 16 】 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMOR

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