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74HC3G16DP PDF预览

74HC3G16DP

更新时间: 2024-11-30 10:47:55
品牌 Logo 应用领域
恩智浦 - NXP 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
14页 155K
描述
HC/UH SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8

74HC3G16DP 技术参数

生命周期:Transferred包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.76系列:HC/UH
JESD-30 代码:S-PDSO-G8长度:3 mm
逻辑集成电路类型:BUFFER功能数量:3
输入次数:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):125 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:3 mm
Base Number Matches:1

74HC3G16DP 数据手册

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74HC3G16; 74HCT3G16  
Triple buffer gate  
Rev. 1 — 15 October 2015  
Product data sheet  
1. General description  
The 74HC3G16; 74HCT3G16 is a triple buffer. Inputs include clamp diodes. This enables  
the use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
Input levels:  
For 74HC3G16: CMOS level  
For 74HCT3G16: TTL level  
Complies with JEDEC standard no. 7 A  
Symmetrical output impedance  
High noise immunity  
Low-power dissipation  
Balanced propagation delays  
Multiple package options  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C and 40 C to +125 C  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC3G16DP  
74HCT3G16DP  
74HC3G16DC  
74HCT3G16DC  
74HC3G16GD  
74HCT3G16GD  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
TSSOP8  
VSSOP8  
XSON8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm; lead length 0.5 mm  
SOT505-2  
plastic very thin shrink small outline package; 8 leads; SOT765-1  
body width 2.3 mm  
plastic extremely thin small outline package; no leads; SOT996-2  
8 terminals; body 3 2 0.5 mm  

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