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74HC3G07DP,125 PDF预览

74HC3G07DP,125

更新时间: 2024-02-22 06:53:32
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管逻辑集成电路
页数 文件大小 规格书
14页 181K
描述
74HC(T)3G07 - Triple buffer with open-drain outputs TSSOP 8-Pin

74HC3G07DP,125 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:3 MM, PLASTIC, SOT505-2, TSSOP-8
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.55
系列:HC/UHJESD-30 代码:S-PDSO-G8
长度:3 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.004 A
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.16
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:25 ns
传播延迟(tpd):125 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mmBase Number Matches:1

74HC3G07DP,125 数据手册

 浏览型号74HC3G07DP,125的Datasheet PDF文件第3页浏览型号74HC3G07DP,125的Datasheet PDF文件第4页浏览型号74HC3G07DP,125的Datasheet PDF文件第5页浏览型号74HC3G07DP,125的Datasheet PDF文件第7页浏览型号74HC3G07DP,125的Datasheet PDF文件第8页浏览型号74HC3G07DP,125的Datasheet PDF文件第9页 
NXP Semiconductors  
74HC3G07; 74HCT3G07  
Triple buffer with open-drain outputs  
Table 8.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 C; for test circuit see Figure 7.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ  
Max  
Min  
Max  
74HCT3G07  
tPZL  
OFF-state to LOW  
propagation delay  
nA to nY; see Figure 6  
VCC = 4.5 V  
-
11  
27  
-
32  
ns  
tPLZ  
LOW to OFF-state  
propagation delay  
nA to nY; see Figure 6  
VCC = 4.5 V  
-
-
10  
6
26  
19  
-
-
31  
22  
ns  
ns  
tTHL  
CPD  
HIGH to LOW output VCC = 4.5 V; see Figure 6  
transition time  
[1]  
power dissipation  
capacitance  
VI = GND to VCC 1.5 V  
-
4
-
-
pF  
[1] CPD is used to determine the dynamic power dissipation (PD in W).  
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL VCC2 fo) = sum of outputs.  
12. Waveforms  
V
I
V
M
nA input  
GND  
t
t
PZL  
PLZ  
V
CC  
nY output  
V
M
V
X
V
OL  
t
THL  
001aak034  
Measurement points are given in Table 9.  
OL is the typical output voltage level that occurs with the output load.  
V
Fig 6. The input (nA) to output (nY) propagation delays  
Table 9.  
Type  
Measurement points  
Input  
Output  
VM  
VM  
VX  
74HC3G07  
0.5 VCC  
1.3 V  
0.5 VCC  
1.3 V  
0.1 VCC  
0.1 VCC  
74HCT3G07  
74HC_HCT3G07  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4 — 16 December 2013  
6 of 14  
 
 
 
 

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