Datasheet > 74HC294

74HC294

更新时间： 2024-11-21 05:34:43

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数据手册

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74HC294 数据手册

M54/74HC292/7292

M54/74HC294/7294

PROGRAMMABLE DIVIDER/TIMER

HIGH SPEED

f_MAX= 70 MHz (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 mA (MAX.) at T_A= 25 ^oC

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

| I_OH|= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

B1R

(Plastic Package)

F1R

(Ceramic Package)

WIDE OPERATING VOLTAGE RANGE

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE WITH

54/74LS292/294

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HCXXXF1R

M74HCXXXB1R

M74HCXXXM1R

M74HCXXXC1R

DESCRIPTION

The 54/74HC292/7292 and HC294/7294 are high

speed CMOS PROGRAMMABLE DIVIDER/TIMER

fabricated with silicon C²MOS technology.

types feature an active-low clear input to initialize

the state of all flip-flops. To facilitate incoming

inspection, test points are provided. (TP1, TP2 and

TP3 on the HC292/7292 and TP on the

HC294/7294). All inputs are equipped with

protection circuits against static discharge and

transient excess voltage.

They achieve the high speed operation similar to

equivalent LSTTL while maintaining the CMOS low

power dissipation.

These devices are programmable frequency

dividers. The typeshave two clockinputs, either one

may be used for clock gating. (see the function

table). The HC292/7292 can divide from 2²to 2³¹,

and the HC294/7294 can divide from 2²to 2¹⁵. The

HC292/294 have Q output with ”Totem pole”

configuration and test point TP with ”Open Drain”

output configuration.

HC7292/7294 have all outputs ”Totem Pole”.

PIN CONNECTION (top view)

HC292

HC7292

HC294

HC7294

HC292

HC7292

HC294

HC7294

October 1993

1/14

12 3 4 5 6 7...14

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