74F632QC

更新时间： 2024-09-10 08:03:31

品牌	Logo	应用领域
美国国家半导体 - NSC		逻辑集成电路
页数	文件大小	规格书
14页	226K
描述
32-Bit Parallel Error Detection and Correction Circuit

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74F632QC 数据手册

May 1991

DP8406 (54F/74F632)

32-Bit Parallel Error Detection and Correction Circuit

General Description

The DP8406 device is a 32-bit parallel error detection and

correction circuit (EDAC) in a 52-pin or 68-pin package. The

EDAC uses a modified Hamming code to generate a 7-bit

check word from a 32-bit data word. This check word is

stored along with the data word during the memory write

cycle. During the memory read cycle, the 39-bit words from

memory are processed by the EDAC to determine if errors

have occurred in memory.

detected. Otherwise, errors in three or more bits of the

39-bit word are beyond the capabilities of these devices to

detect.

Read-modify-write (byte-control) operations can be per-

formed by using output latch enable, LEDBO, and the indi-

vidual OEB through OEB byte control pins.

Diagnostics are performed on the EDACs by controls and

internal paths that allow the user to read the contents of the

Data Bit and Check Bit input latches. These will determine if

the failure occurred in memory or in the EDAC.

Single-bit errors in the 32-bit data word are flagged and cor-

rected.

Single-bit errors in the 7-bit check word are flagged, and the

CPU sends the EDAC through the correction cycle even

though the 32-bit data word is not in error. The correction

cycle will simply pass along the original 32-bit data word in

this case and produce error syndrome bits to pinpoint the

error-generating location.

Features

Detects and corrects single-bit errors

Detects and flags dual-bit errors

Built-in diagnostic capability

Fast write and read cycle processing times

Dual-bit errors are flagged but not corrected. These errors

may occur in any two bits of the 39-bit word from memory

(two errors in the 32-bit data word, two errors in the 7-bit

check word, or one error in each word). The gross-error

condition of all LOWs or all HIGHs from memory will be

Byte-write capability

Guaranteed 4000V minimum ESD protection

Fully pin and function compatible with TI’s

SN74ALS632A thru SN74ALS635 series

Simplified Functional Block

TL/F/9579–9

Device

DP8406

Package

52-Pin

Byte-Write

Output

TRI-STATE

yes

68-Pin

FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/9579

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...14

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与74F632QC相关器件

型号	品牌	获取价格	描述	数据表
74F632QCQR	FAIRCHILD	获取价格	Error Detection And Correction Circuit, F/FAST Series, 32-Bit, TTL, PQCC52, PLASTIC, LCC-5
74F632QCQR	TI	获取价格	F/FAST SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQCC52, PLASTIC, LCC-52
74F632VC	NSC	获取价格	32-Bit Parallel Error Detection and Correction Circuit
74F632VCQR	TI	获取价格	F/FAST SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQCC68, PLASTIC, LCC-68
74F64	NXP	获取价格	4-2-3-2-input AND-OR-invert gate
74F64	FAIRCHILD	获取价格	4-2-3-2-Input AND-OR-Invert Gate
74F64	NSC	获取价格	4-2-3-2-Input AND-OR-Invert Gate
74F640	FAIRCHILD	获取价格	Octal Bus Transceiver with 3-STATE Outputs
74F640	NXP	获取价格	Octal bus transceiver, inverting 3-State
74F640PC	FAIRCHILD	获取价格	Octal Bus Transceiver with 3-STATE Outputs

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