SN74CBTK6800
10-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS
AND ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS107B – APRIL 2000 – REVISED OCTOBER 2000
DBQ, DGV, DW, OR PW PACKAGE
5-Ω Switch Connection Between Two Ports
(TOP VIEW)
TTL-Compatible Input Levels
Power Off Disables Outputs, Permitting
Live Insertion
1
24
23
22
21
20
19
18
17
16
15
14
13
ON
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
B1
2
3
B2
B3
B4
B5
B6
B7
B8
B9
Outputs Are Precharged by Bias Voltage to
Minimize Signal Distortion During Live
Insertion
4
5
6
Active-Clamp Undershoot-Protection
Circuit on the I/Os Clamps Undershoots
Down to –2 V
7
8
9
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
10
11
12
A9
A10
GND
B10
BIASV
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74CBTK6800 device provides ten bits of high-speed TTL-compatible bus switching. The low on-state
resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay.
ThedevicealsoprechargestheBporttoauser-selectablebiasvoltage(BIASV)tominimizelive-insertionnoise.
The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the
active-clamp circuit is enabled and current from V
transistor from turning on.
is supplied to clamp the output, preventing the pass
CC
The SN74CBTK6800 is organized as one 10-bit switch with a single enable (ON) input. When ON is low, the
switch is on, and port A is connected to port B. When ON is high, the switch between port A and port B is open.
When ON is high or V
is 0 V, B port is precharged to BIASV through the equivalent of a 10-kΩ resistor.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBTK6800DW
SN74CBTK6800DWR
SN74CBTK6800DBQR
SN74CBTK6800PWR
SN74CBTK6800DGVR
SOIC – DW
CBTK6800
Tape and reel
–40°C to 85°C SSOP (QSOP) – DBQ Tape and reel
CBTK6800
BK6800
TSSOP – PW
TVSOP – DGV
Tape and reel
Tape and reel
BK6800
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
FUNCTION
ON
L
A port = B port
A port = Z
B port = BIASV
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265