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74CBTLV16211GRE4 PDF预览

74CBTLV16211GRE4

更新时间: 2024-11-06 03:07:43
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德州仪器 - TI 开关
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10页 172K
描述
LOW-VOLTAGE 24-BIT FET BUS SWITCH

74CBTLV16211GRE4 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢉꢉ  
ꢇ ꢌꢍꢎꢈꢌ ꢇꢆꢏꢐ ꢑ ꢋ ꢃ ꢎꢅꢒ ꢆ ꢓ ꢑꢆ ꢅꢔ ꢀ ꢀ ꢍꢒ ꢆꢄ ꢕ  
SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
Member of the Texas Instruments  
WidebusFamily  
D
D
D
D
D
5-Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
1
56  
55  
54  
53  
52  
51  
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33  
32  
31  
30  
29  
NC  
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
1A9  
1A10  
1A11  
1A12  
2A1  
2A2  
1OE  
2OE  
1B1  
1B2  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
1B9  
1B10  
1B11  
1B12  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
2B7  
2B8  
2B9  
2B10  
2B11  
2B12  
2
3
I
Supports Partial-Power-Down Mode  
off  
4
Operation  
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
7
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
8
9
10  
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24  
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28  
description/ordering information  
The SN74CBTLV16211 provides 24 bits of  
high-speed bus switching. The low on-state  
resistance of the switch allows connections to be  
made with minimal propagation delay.  
V
CC  
The device is organized as dual 12-bit bus  
switches with separate output-enable (OE)  
inputs. It can be used as two 12-bit bus switches  
or as one 24-bit bus switch. When OE is low, the  
associated 12-bit bus switch is on, and port A is  
connected to port B. When OE is high, the switch  
is open, and the high-impedance state exists  
between the two ports.  
2A3  
GND  
2A4  
2A5  
2A6  
2A7  
2A8  
2A9  
This  
device  
is  
fully  
specified  
for  
2A10  
2A11  
2A12  
partial-power-down applications using I . The I  
off  
off  
feature ensures that damaging current will not  
backflow through the device when it is powered  
down. The device has isolation during power off.  
NC − No internal connection  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74CBTLV16211DL  
SN74CBTLV16211DLR  
SN74CBTLV16211GR  
SN74CBTLV16211VR  
SSOP − DL  
CBTLV16211  
Tape and reel  
−40°C to 85°C  
TSSOP − DGG Tape and reel  
TVSOP − DGV Tape and reel  
CBTLV16211  
CN211  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢆꢤ  
Copyright 2003, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74CBTLV16211GRE4 替代型号

型号 品牌 替代类型 描述 数据表
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