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74AVC16834DGVRE4 PDF预览

74AVC16834DGVRE4

更新时间： 2024-11-06 15:26:35
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路电视
页数 文件大小 规格书
17页 359K
描述
18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85

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74AVC16834DGVRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP, TSSOP56,.25,16针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.59控制类型：ENABLE LOW
系列：AVCJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：11.3 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.1 ns传播延迟（tpd）：7.8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.4 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

74AVC16834DGVRE4 数据手册

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SN74AVC16834  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES183H–DECEMBER 1998–REVISED JUNE 2005  
FEATURES  
•
•
•
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
•
Member of the Texas Instruments Widebus™  
Family  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
DOC™ (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without Speed  
Degradation  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With IOH and IOL of ±24 mA  
at 2.5-V VCC  
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
DESCRIPTION/ORDERING INFORMATION  
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows  
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At  
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a  
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family  
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry  
Technology and Applications, literature number SCEA009.  
3.2  
T
A
= 25°C  
T
A
= 25°C  
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
CC  
= 3.3 V  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
CC  
= 2.5 V  
V
CC  
= 1.8 V  
V
CC  
= 3.3 V  
V
CC  
= 2.5 V  
V
CC  
= 1.8 V  
0
17  
34  
51  
68  
85 102 119 136 153 170  
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16  
- Output Current - mA  
0
I
- Output Current - mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to  
3.6-V VCC operation.  
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode  
when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low  
logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is  
high, the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, DOC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1998–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 
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74AVC16834DGVRE4 替代型号

型号 品牌 替代类型 描述 数据表
74AVC16834DGGRE4 TI

完全替代

 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
74AVC16834DGVRG4 TI

完全替代

 18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85
SN74AVC16834DGVR TI

功能相似

 具有三态输出的 18 位通用总线驱动器 | DGV | 56 | -40 to 85

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74AVC16835ADGG,112 NXP

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 		74AVC16835A - 18-bit registered driver with Dynamic Controlled Outputs(TM) (3-State) TSSOP
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74AVC16835ADGV ETC

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74AVC16835ADGV,112 NXP

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 		74AVC16835A - 18-bit registered driver with Dynamic Controlled Outputs(TM) (3-State) TSSOP

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