Datasheet > 74AUP2G125GN,115

74AUP2G125GN,115

更新时间： 2024-11-16 14:47:03

品牌	Logo	应用领域
恩智浦 - NXP		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
24页	305K
描述
74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin

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74AUP2G125GN,115 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SON
包装说明：	1.20 X 1 MM, 0.35 MM HEIGHT, SOT-1116, SON-8	针数：	8
Reach Compliance Code：	compliant	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

74AUP2G125GN,115 数据手册

74AUP2G125

Low-power dual buffer/line driver; 3-state

Rev. 10 — 8 February 2013

Product data sheet

1. General description

The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE

causes the output to assume a high-impedance OFF-state. This device has the

input-disable feature, which allows floating input signals. The inputs are disabled when the

output enable input nOE) is HIGH.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V. This device ensures a very low

static and dynamic power consumption across the entire V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD78B Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 Input-disable feature allows floating input conditions

 I_OFFcircuitry provides partial power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...24

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与74AUP2G125GN,115相关器件

型号	品牌	获取价格	描述	数据表
74AUP2G125GS	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GS	NEXPERIA	获取价格	Low-power dual buffer/line driver; 3-stateProduction
74AUP2G125GS,115	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin
74AUP2G125GT	NXP	获取价格	Low-power dual buffer/line driver; 3-state
74AUP2G125GT	NEXPERIA	获取价格	Low-power dual buffer/line driver; 3-stateProduction
74AUP2G125GT,115	NXP	获取价格	74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin
74AUP2G125GX	NEXPERIA	获取价格	Low-power dual buffer/line driver; 3-stateProduction
74AUP2G126	NXP	获取价格	Low-power dual buffer/line driver
74AUP2G126	DIODES	获取价格	Dual 3-State Buffer OE LOW
74AUP2G126DC	NXP	获取价格	Low-power dual buffer/line driver

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