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74AUP2G125GS PDF预览

74AUP2G125GS

更新时间: 2024-11-17 11:12:15
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
23页 322K
描述
Low-power dual buffer/line driver; 3-stateProduction

74AUP2G125GS 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.59
系列:AUP/ULP/VJESD-30 代码:R-PDSO-N8
JESD-609代码:e3长度:1.35 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:1功能数量:2
端口数量:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):24 ns
认证状态:Not Qualified座面最大高度:0.35 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.35 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74AUP2G125GS 数据手册

 浏览型号74AUP2G125GS的Datasheet PDF文件第2页浏览型号74AUP2G125GS的Datasheet PDF文件第3页浏览型号74AUP2G125GS的Datasheet PDF文件第4页浏览型号74AUP2G125GS的Datasheet PDF文件第5页浏览型号74AUP2G125GS的Datasheet PDF文件第6页浏览型号74AUP2G125GS的Datasheet PDF文件第7页 
74AUP2G125  
Low-power dual buffer/line driver; 3-state  
Rev. 14 — 21 June 2022  
Product data sheet  
1. General description  
The 74AUP2G125 is a dual buffer/line driver with 3-state outputs controlled by the output enable  
inputs (nOE). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and  
fall times. This device ensures very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
CMOS low power dissipation  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD78B Class II  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
Input-disable feature allows floating input conditions  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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