74AUP1G386
NXP Semiconductors
Low-power 3-input EXCLUSIVE-OR gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
plastic surface-mounted package; 6 leads
Version
74AUP1G386GW
74AUP1G386GM
40 C to +125 C
40 C to +125 C
SC-88
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
74AUP1G386GF
74AUP1G386GN
74AUP1G386GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON6
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
SOT1202
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G386GW
74AUP1G386GM
74AUP1G386GF
74AUP1G386GN
74AUP1G386GS
aH
aH
aH
aH
aH
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
A
1
Y
B
1
3
6
= 1
4
3
6
4
C
mnb143
mnb145
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AUP1G386
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 28 November 2011
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