5秒后页面跳转
74AUP1G00GW PDF预览

74AUP1G00GW

更新时间: 2024-11-28 11:11:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
18页 273K
描述
Low-power 2-input NAND gateProduction

74AUP1G00GW 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.16
Is Samacsys:N系列:AUP/ULP/V
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2.05 mm逻辑集成电路类型:NAND GATE
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):24.9 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.25 mm
Base Number Matches:1

74AUP1G00GW 数据手册

 浏览型号74AUP1G00GW的Datasheet PDF文件第2页浏览型号74AUP1G00GW的Datasheet PDF文件第3页浏览型号74AUP1G00GW的Datasheet PDF文件第4页浏览型号74AUP1G00GW的Datasheet PDF文件第5页浏览型号74AUP1G00GW的Datasheet PDF文件第6页浏览型号74AUP1G00GW的Datasheet PDF文件第7页 
74AUP1G00  
Low-power 2-input NAND gate  
Rev. 9.1 — 11 July 2023  
Product data sheet  
1. General description  
The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the  
circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic  
power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified  
for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the  
damaging backflow current through the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

74AUP1G00GW 替代型号

型号 品牌 替代类型 描述 数据表
NC7SP00P5X ONSEMI

功能相似

TinyLogic ULP 2输入NAND门

与74AUP1G00GW相关器件

型号 品牌 获取价格 描述 数据表
74AUP1G00GW-Q100 NEXPERIA

获取价格

Low-power 2-input NAND gateProduction
74AUP1G00GX NEXPERIA

获取价格

Low-power 2-input NAND gateProduction
74AUP1G00SE DIODES

获取价格

SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G00SE-7 DIODES

获取价格

SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G02 DIODES

获取价格

SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G02 NXP

获取价格

Low-power 2-input NOR gate
74AUP1G02FW4-7 DIODES

获取价格

SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G02FZ4-7 DIODES

获取价格

SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G02GF NXP

获取价格

Low-power 2-input NOR gate
74AUP1G02GF,132 NXP

获取价格

74AUP1G02 - Low-power 2-input NOR-gate SON 6-Pin