5秒后页面跳转
捷配首页

Datasheet > 74AUCH16374DGGRE4
74AUCH16374DGGRE4 PDF预览

74AUCH16374DGGRE4

更新时间： 2024-02-01 06:51:56
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 822K
描述
AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48

阅读下载

中文翻译

获取价格

74AUCH16374DGGRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.54系列：AUC
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：250000000 Hz
最大I（ol）：0.005 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
Prop。Delay @ Nom-Sup：4.5 ns传播延迟（tpd）：4.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74AUCH16374DGGRE4 数据手册

 浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第2页浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第3页浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第4页浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第5页浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第6页浏览型号74AUCH16374DGGRE4的Datasheet PDF文件第7页 
SN74AUCH16374  
www.ti.com  
SCES404E –JULY 2002–REVISED JULY 2012  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
Check for Samples: SN74AUCH16374  
1
FEATURES  
DGG OR DGV PACKAGE  
(TOP VIEW)  
2
•
Member of the Texas Instruments Widebus™  
Family  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
VCC  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
VCC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
VCC  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
VCC  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
2
3
4
•
Ioff Supports Partial-Power-Down Mode  
Operation  
5
6
•
•
•
•
•
Sub-1-V Operable  
7
Max tpd of 2.8 ns at 1.8 V  
8
Low Power Consumption, 20 μA Max ICC  
±8-mA Output Drive at 1.8 V  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit edge-triggered D-type flip-flop is  
operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive  
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D)  
inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2012, Texas Instruments Incorporated  
1234567...18

中文翻译

下载PDF

与74AUCH16374DGGRE4相关器件

型号 品牌 获取价格 描述 数据表
74AUCH16374DGVRG4 TI

获取价格

 		AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TVSOP-48
74AUP1G00 NXP

获取价格

 		Low-power 2-input NAND gate
74AUP1G00 DIODES

获取价格

 		SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G00FW4-7 DIODES

获取价格

 		SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G00FZ4-7 DIODES

获取价格

 		SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G00GF NXP

获取价格

 		Low-power 2-input NAND gate
74AUP1G00GF,132 NXP

获取价格

 		74AUP1G00 - Low-power 2-input NAND gate SON 6-Pin
74AUP1G00GM NXP

获取价格

 		Low-power 2-input NAND gate
74AUP1G00GM NEXPERIA

获取价格

 		Low-power 2-input NAND gateProduction
74AUP1G00GN NXP

获取价格

 		AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6

与74AUCH16374DGGRE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证