Datasheet > 74ALVT16827DL,112

74ALVT16827DL,112

更新时间： 2024-11-04 13:40:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	87K
描述
74ALVT16827 - 20-bit buffer/line driver; non-inverting; 3-state SSOP 56-Pin

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74ALVT16827DL,112 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	生命周期：	Transferred
零件包装代码：	SSOP	包装说明：	7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
针数：	56	Reach Compliance Code：	unknown
风险等级：	5.7	Base Number Matches：	1

74ALVT16827DL,112 数据手册

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74ALVT16827

20-bit buffer/line driver; non-inverting; 3-state

Rev. 03 — 2 June 2005

Product data sheet

1. General description

The 74ALVT16827 high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive. It is designed for V_CCoperation

at 2.5 V or 3.3 V with I/O compatibility to 5 V.

The 74ALVT16827 20-bit buffers provide high performance bus interface buffering for wide

data/address paths or buses carrying parity. They have NOR Output Enables (nOE1 and

nOE2) for maximum control ﬂexibility.

2. Features

■ Multiple V_CCand GND pins minimize switching noise

■ 5 V I/O compatible

■ Live insertion and extraction permitted

■ 3-state output buffers

■ Power-up 3-state

■ Output capability: +64 mA and −32 mA

■ Latch-up protection:

◆ JESD 78 exceeds 500 mA

■ ElectroStatic Discharge (ESD) protection:

◆ MIL STD 883 Method 3015: exceeds 2000 V

◆ Machine model: exceeds 200 V

■ Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C.

Symbol Parameter

Conditions

Min

1.0

0.7

1.0

0.8

Typ

2.0

1.5

2.0

1.6

Max

2.9

2.2

3.0

2.3

Unit

t_PLH

t_PHL

C_I

propagation delay nAx C_L= 50 pF; V_CC= 2.5 V

to nYx

C_L= 50 pF; V_CC= 3.3 V

propagation delay nAx C_L= 50 pF; V_CC= 2.5 V

to nYx

C_L= 50 pF; V_CC= 3.3 V

input capacitance on V_I= 0 V or V_CC

DIR, OE

12 3 4 5 6 7...16

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