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74ALVCH16600DGGRE4 PDF预览

74ALVCH16600DGGRE4

更新时间： 2024-09-16 14:48:43
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 312K
描述
IC ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56, Bus Driver/Transceiver

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74ALVCH16600DGGRE4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：unknown
风险等级：5.53其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：7.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：NEGATIVE EDGE
宽度：6.1 mmBase Number Matches：1

74ALVCH16600DGGRE4 数据手册

 浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第2页浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第3页浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第4页浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第5页浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第6页浏览型号74ALVCH16600DGGRE4的Datasheet PDF文件第7页 
SN74ALVCH16600  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES030G–JULY 1995–REVISED JULY 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, or  
Clock-Enable Mode  
2
3
4
5
•
•
•
•
Operates From 1.65-V to 3.6-V VCC  
Max tpd of 4 ns at 3.3-V VCC  
6
A3  
B3  
7
V
CC  
V
CC  
±24-mA Output Drive at 3.3-V VCC  
8
A4  
A5  
A6  
GND  
A7  
A8  
B4  
B5  
B6  
GND  
B7  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
B8  
ESD Performance Tested Per JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
A9  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
DESCRIPTION/ORDERING INFORMATION  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16600 combines D-type latches and  
D-type flip-flops to allow data flow in transparent,  
latched, and clocked modes.  
V
CC  
V
CC  
A16  
A17  
B16  
B17  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For  
A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When LEAB is  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
CLKENBA  
low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the  
latch/flip-flop on the high-to-low transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is  
high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA,  
LEBA, CLKBA, and CLKENBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH16600DL  
TOP-SIDE MARKING  
ALVCH16600  
Tube  
SSOP - DL  
-40 to 85°C  
Tape and reel  
Tape and reel  
SN74ALVCH16600DLR  
TSSOP - DGG  
SN74ALVCH16600DGGR  
ALVCH16600  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

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