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74ALVCH16540PA PDF预览

74ALVCH16540PA

更新时间: 2024-11-10 10:15:55
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
6页 77K
描述
TSSOP-48, Tube

74ALVCH16540PA 数据手册

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IDT74ALVCH16540  
3.3V CMOS 16-BIT INVERTING  
BUFFER/LINE DRIVER  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
This 16-bit inverting buffer/line driver is built using advanced dual metal  
CMOStechnology.TheALVCH16540offersbus/backplaneinterfacecapabil-  
itywithimprovedpackingdensityandaflow-throughorganizationforsimplifying  
boardlayout.Itisdesignedspecificallytoimprovetheperformanceanddensity  
of3-statememoryaddressdrivers,clockdrivers,andbus-orientedreceivers  
andtransmitters.Thethree-statecontrolsoperatethisdeviceinaquad-nibble,  
dual-byte,orsingle16-bitwordmode.The3-stateoutputsarecontrolledbythe  
output enable (OE) pins. A high on OE causes the outputs to force a high  
impedanceoff-state.Allinputsaredesignedwithhysteresisforimprovednoise  
margin.  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in SSOP, TSSOP, and TVSOP packages  
The ALVCH16540 has been designed with a ±24mA output driver. This  
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed  
performance.  
The ALVCH16540 has “bus-hold” which retains the inputs’ last state  
whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs  
andeliminatestheneedforpull-up/downresistors.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Suitable for heavy loads  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
2
47  
6  
35  
13  
14  
1
2A1  
2Y0  
2Y1  
1A0  
46  
5
1Y1  
1Y2  
3  
1Y4  
1A1  
44  
43  
41  
33  
32  
16  
17  
19  
2A2  
2A3  
2A4  
2Y2  
2Y3  
1A2  
1A3  
30  
2Y4  
1A4  
9
20  
29  
27  
26  
2Y5  
2Y6  
2Y7  
1Y5  
1Y6  
1Y7  
1A5  
1A6  
1A7  
2A5  
2A6  
2A7  
11  
12  
22  
23  
38  
37  
24  
25  
2OE1  
2OE2  
1OE1  
1OE2  
48  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4545/1  

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