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74ALVC16244GX PDF预览

74ALVC16244GX

更新时间: 2024-11-08 22:16:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器逻辑集成电路
页数 文件大小 规格书
8页 120K
描述
Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

74ALVC16244GX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA54,6X9,32
针数:54Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.45
控制类型:ENABLE LOW系列:ALVC/VCX/A
JESD-30 代码:R-PBGA-B54JESD-609代码:e0
长度:8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:3位数:4
功能数量:4端口数量:2
端子数量:54最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA54,6X9,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:3 ns
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:1.4 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.5 mm
Base Number Matches:1

74ALVC16244GX 数据手册

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October 2001  
Revised May 2005  
74ALVC16244  
Low Voltage 16-Bit Buffer/Line Driver  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The ALVC16244 contains sixteen non-inverting buffers with  
Features  
3-STATE outputs to be employed as  
a memory and  
1.65V–3.6V VCC supply operation  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
3.6V tolerant inputs and outputs  
tPD  
3.0 ns max for 3.0V to 3.6V VCC  
3.5 ns max for 2.3V to 2.7V VCC  
6.0 ns max for 1.65V to 1.95V VCC  
The 74ALVC16244 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
The 74ALVC16244 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
Uses patented noise/EMI reduction circuitry  
Latch-up conforms to JEDEC JED98  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74ALVC16244GX  
(Note 2)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[Tape and Reel]  
74ALVC16244MTD  
(Note 3)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: BGA package available in Tape and Reel only.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS500677  
www.fairchildsemi.com  

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